//8bit补码
//正数补码不变
//负数补码取反加一
module complement (
    a,
    a_comp
);
input[7:0] a;
output[7:0] a_comp;

wire[7:0] y;//取反加一
assign y[6:0]=(~a[6:0])+1;
assign y[7]=1;
//assign y={1'b1,(~a[6:0])+1};  位拼接

assign a_comp=a[7]?y:a;

endmodule

//tb
`timescale 1ns/10ps
module complement_tb ();
reg[7:0] aa;
wire[7:0] ac;
complement complement (
    .a(aa),
    .a_comp(ac)
); 
initial begin
            aa<=0;
    #3000   $stop;
end
always begin
    #10 aa<=aa+1;
end
endmodule
